`include "common_header.verilog"

//  *************************************************************************
//   File : top_xgxs_w_host.v
//  *************************************************************************
//   This program is controlled by a written license agreement.
//   Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2005 Morethanip GmbH
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: top_xgxs_w_host.v,v 1.4 2013/02/12 10:28:09 mr Exp $ 
//  Author : Muhammad Anisur Rahman
//  *************************************************************************
//   Description:
// 
//   10 Gigabit Ethernet XGXS PCS Top-Level with host interface
// 
//  *************************************************************************
module top_xgxs_w_host (
   reset_sd0_rx_clk,
   reset_sd1_rx_clk,
   reset_sd2_rx_clk,
   reset_sd3_rx_clk,
   reset_xgmii_txclk,
   reset_xgmii_rxclk,
   xgmii_txclk,
`ifdef USE_CLK_ENA
   xgmii_txclk_ena,
`endif   
   xgmii_txd,
   xgmii_txc,
   xgmii_rxclk,
`ifdef ENA_RX_RATE_MATCHING   
`ifdef USE_CLK_ENA
   xgmii_rxclk_ena,
`endif 
   jumbo_en,
`endif   
   xgmii_rxd,
   xgmii_rxc,
   sd0_tx,
   sd1_tx,
   sd2_tx,
   sd3_tx,
   sd0_rx,
   sd0_rx_clk,
`ifdef USE_CLK_ENA
   sd0_rx_clk_ena,
`endif   
   sd1_rx,
   sd1_rx_clk,
`ifdef USE_CLK_ENA
   sd1_rx_clk_ena,
`endif   
   sd2_rx,
   sd2_rx_clk,
`ifdef USE_CLK_ENA
   sd2_rx_clk_ena,
`endif   
   sd3_rx,
   sd3_rx_clk,
`ifdef USE_CLK_ENA
   sd3_rx_clk_ena,
`endif   
   sd_signal0,
   sd_signal1,
   sd_signal2,
   sd_signal3,
  `ifdef MTIPXGXS_BUFRESET
   buf_reset,
  `endif    
   align_done,
   disp_err,
   char_err,
   cg_align,
   sync,
   pat,
   match_fault,   
   reset_reg_clk,
   reg_clk,
   reg_rd,
   reg_wr,
   reg_addr,
   reg_din,
   reg_dout,
   reg_busy);

`include "mtip_xgxs_package.verilog"
   
input   reset_sd0_rx_clk;       //  Asynchronous Reset - sd0_rx_clk Domain
input   reset_sd1_rx_clk;       //  Asynchronous Reset - sd1_rx_clk Domain
input   reset_sd2_rx_clk;       //  Asynchronous Reset - sd2_rx_clk Domain
input   reset_sd3_rx_clk;       //  Asynchronous Reset - sd3_rx_clk Domain
input   reset_xgmii_txclk;      //  Asynchronous Reset - xgmii_txclk Domain       
input   reset_xgmii_rxclk;      //  Asynchronous Reset - xgmii_rxclk Domain       
input   xgmii_txclk;            //  156.25MHz Transmit Clock
input   [63:0] xgmii_txd;       //  Transmit Data
input   [7:0] xgmii_txc;        //  Transmit Control
output  [63:0] xgmii_rxd;       //  Receive Data
output  [7:0] xgmii_rxc;        //  Receive Control        
output  [19:0] sd0_tx;          //  SERDES Lane 0
output  [19:0] sd1_tx;          //  SERDES Lane 1
output  [19:0] sd2_tx;          //  SERDES Lane 2
output  [19:0] sd3_tx;          //  SERDES Lane 3
input   [19:0] sd0_rx;          //  SERDES Lane 0
input   sd0_rx_clk;             //  SERDES Lane 0 Clock
input   [19:0] sd1_rx;          //  SERDES Lane 1
input   sd1_rx_clk;             //  SERDES Lane 1 Clock
input   [19:0] sd2_rx;          //  SERDES Lane 2
input   sd2_rx_clk;             //  SERDES Lane 2 Clock
input   [19:0] sd3_rx;          //  SERDES Lane 3
input   sd3_rx_clk;             //  SERDES Lane 3 Clock
input   sd_signal0;             //  SERDES Lane 0 Status        
input   sd_signal1;             //  SERDES Lane 1 Status        
input   sd_signal2;             //  SERDES Lane 2 Status        
input   sd_signal3;             //  SERDES Lane 3 Status
`ifdef MTIPXGXS_BUFRESET
   output [3:0] buf_reset;      //  Rset buffers when deskew error occured
`endif
output  align_done;             //  Lane Alignment Done
output  [3:0] disp_err;         //  Disparity Error Indication
output  [3:0] char_err;         //  Character Error Indication
output  [3:0] sync;             //  Channel Synchronization Indication
output  [3:0] pat;              //  Comma Detected Indication
output  [3:0] cg_align;         //  Code Group Alignment Indication
output  match_fault;            //  Rate Matching Error Indication
`ifdef USE_CLK_ENA
   input xgmii_txclk_ena;       // Enable xgmii_txclk
   input sd0_rx_clk_ena;        // Enable sd0_rx_clk
   input sd1_rx_clk_ena;        // Enable sd1_rx_clk
   input sd2_rx_clk_ena;        // Enable sd2_rx_clk
   input sd3_rx_clk_ena;        // Enable sd3_rx_clk
`endif 
`ifdef ENA_RX_RATE_MATCHING
  `ifdef USE_CLK_ENA
   input   xgmii_rxclk_ena;
  `endif   
 input   jumbo_en;               //  increase thresholds(=latency) to support jumbo frames
`endif 
input   reset_reg_clk;          //  Asynchronous Reset - reg_clk Domain                
input   reg_clk;                //  ReferenceInterface Clock        
input   reg_rd;                 //  Register Read Strobe
input   reg_wr;                 //  Register Write Strobe
input   [15:0] reg_addr;        //  Register Address
input   [15:0] reg_din;         //  Write Data for Host Bus
output  [15:0] reg_dout;        //  Read Data to Host Bus   
output  reg_busy;               //  Acknowledgement for read/ write operation                                        

//  ------------- --
//  Reset Signals --
//  ------------- --
//  SERDES Interface
//  ----------------
wire    xgmii_rxclk_int; 

`ifdef ENA_RX_RATE_MATCHING

   input   xgmii_rxclk;         //  156.25MHz Receive Clock    
   
   assign xgmii_rxclk_int = xgmii_rxclk ;

`else

   output xgmii_rxclk;          //  156.25MHz Receive Clock output

   wire   xgmii_rxclk;

   assign xgmii_rxclk     = xgmii_rxclk_int ;

`endif

wire    [63:0] xgmii_rxd; 
//  ---------------- --
//  SERDES Interface --
//  ---------------- --
//  Transmit
//  --------
wire    [7:0] xgmii_rxc; 
wire    [19:0] sd0_tx; 
wire    [19:0] sd1_tx; 
wire    [19:0] sd2_tx; 
wire    [19:0] sd3_tx; 
`ifdef MTIPXGXS_BUFRESET
wire    [3:0] buf_reset;      //  Reset buffers when deskew error occured
`endif
wire    align_done; 
wire    [3:0] disp_err;
wire    [3:0] char_err;  
wire    [3:0] sync; 
wire    [3:0] pat; 
wire    [3:0] cg_align;
wire    match_fault; 
wire    [15:0] reg_dout; 
wire    reg_busy; 
wire    align_done_int; 
wire    [3:0] disp_err_int; 
wire    [3:0] sync_int; 
wire    [3:0] pat_int; 
wire    match_fault_int; 
wire    jumbo_en; 
wire    [3:0] cg_align_int; 
wire    [3:0] char_err_int; 
wire    tx_err; 
wire    sw_reset; 

wire    [1:0] ext_control; // Extended vendor specific control (unused)

top_xgxs u_xgxs (
          .reset_sd0_rx_clk(reset_sd0_rx_clk),
          .reset_sd1_rx_clk(reset_sd1_rx_clk),
          .reset_sd2_rx_clk(reset_sd2_rx_clk),
          .reset_sd3_rx_clk(reset_sd3_rx_clk),
          .reset_xgmii_txclk(reset_xgmii_txclk),
          .reset_xgmii_rxclk(reset_xgmii_rxclk),
          .xgmii_txclk(xgmii_txclk),
        `ifdef USE_CLK_ENA
          .xgmii_txclk_ena(xgmii_txclk_ena),
        `endif          
          .xgmii_txd(xgmii_txd),
          .xgmii_txc(xgmii_txc),
          .xgmii_rxclk(xgmii_rxclk_int),
        `ifdef ENA_RX_RATE_MATCHING   
        `ifdef USE_CLK_ENA
          .xgmii_rxclk_ena(xgmii_rxclk_ena),
        `endif 
          .jumbo_en(jumbo_en),
        `endif          
          .xgmii_rxd(xgmii_rxd),
          .xgmii_rxc(xgmii_rxc),
          .sd0_tx(sd0_tx),
          .sd1_tx(sd1_tx),
          .sd2_tx(sd2_tx),
          .sd3_tx(sd3_tx),
          .sd0_rx(sd0_rx),
          .sd0_rx_clk(sd0_rx_clk),
        `ifdef USE_CLK_ENA
          .sd0_rx_clk_ena(sd0_rx_clk_ena),
        `endif          
          .sd1_rx(sd1_rx),
          .sd1_rx_clk(sd1_rx_clk),
        `ifdef USE_CLK_ENA
          .sd1_rx_clk_ena(sd1_rx_clk_ena),
        `endif          
          .sd2_rx(sd2_rx),
          .sd2_rx_clk(sd2_rx_clk),
        `ifdef USE_CLK_ENA
          .sd2_rx_clk_ena(sd2_rx_clk_ena),
        `endif          
          .sd3_rx(sd3_rx),
          .sd3_rx_clk(sd3_rx_clk),
        `ifdef USE_CLK_ENA
          .sd3_rx_clk_ena(sd3_rx_clk_ena),
        `endif          
          .sd_signal0(sd_signal0),
          .sd_signal1(sd_signal1),
          .sd_signal2(sd_signal2),
          .sd_signal3(sd_signal3),
          `ifdef MTIPXGXS_BUFRESET
          .buf_reset(buf_reset),
          `endif             
          .align_done(align_done_int),
          .disp_err(disp_err_int),
          .char_err(char_err_int),
          .cg_align(cg_align_int),
          .sync(sync_int),
          .pat(pat_int),
          .match_fault(match_fault_int));

assign align_done = align_done_int; 
assign disp_err = disp_err_int;
assign char_err = char_err_int;
assign cg_align = cg_align_int;
assign sync = sync_int; 
assign pat = pat_int; 
assign match_fault = match_fault_int;
//assign jumbo_en = 1'b 1;
assign tx_err = 1'b 0; //  implementation dependent(error on transmit path)


register_map_xgxs u_host_cntrl (
          .reset_rx_clk(reset_xgmii_rxclk),
          .reset_tx_clk(reset_xgmii_txclk),
	  .reset_sd0_rx_clk(reset_sd0_rx_clk),
	  .reset_sd1_rx_clk(reset_sd1_rx_clk),
	  .reset_sd2_rx_clk(reset_sd2_rx_clk),
	  .reset_sd3_rx_clk(reset_sd3_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .reg_clk(reg_clk),
          .rx_clk(xgmii_rxclk_int),
          .tx_clk(xgmii_txclk),
	  .sd0_rx_clk(sd0_rx_clk),
	  .sd1_rx_clk(sd1_rx_clk),
	  .sd2_rx_clk(sd2_rx_clk),
	  .sd3_rx_clk(sd3_rx_clk),
	  .tx_err(tx_err),
	  .sd_signal0(sd_signal0),
	  .sd_signal1(sd_signal1),
	  .sd_signal2(sd_signal2),
	  .sd_signal3(sd_signal3),
	  .ext_control(ext_control),
          .link_status(align_done_int),
          .align_done(align_done_int),
          .sync(sync_int),
          .cg_align(cg_align_int),
          .char_err(char_err_int),
          .disp_err(disp_err_int),
          .comma_detect(pat_int),
          .match_fault(match_fault_int),
          .jumbo_en(jumbo_en),
          .reg_rd(reg_rd),
          .reg_wr(reg_wr),
          .reg_addr(reg_addr),
          .reg_din(reg_din),
          .reg_dout(reg_dout),
          .reg_busy(reg_busy),
          .sw_reset(sw_reset));


endmodule // module top_xgxs_w_host

